(a) Field of the Invention
The present invention relates to a plasma display panel (PDP) and a method for driving the same. More specifically, the present invention relates to a sustain discharge circuit that directly distributes the light emission of the PDP and a method for driving the same.
(b) Description of the Related Art
A flat panel display such as a liquid crystal display (LCD), a field emission display (FED), and a plasma display panel (PDP) has recently been actively developed. Among the flat panel displays, the PDP has brightness and luminous efficiency that are higher than those of the other flat panel displays, and a viewing angle wider than those of the other flat panel displays. Therefore, the PDP is spotlighted as a display that can replace a conventional cathode ray tube (CRT) in a more than 40-inch large display.
The PDP is a flat panel display for displaying characters or images using plasma generated by gas discharge. Pixels ranging from hundreds of thousands to more than millions are arranged in the form of a matrix according to the size of the PDP. PDPs are divided into a direct current (DC) PDP and an alternating current (AC) PDP according to the shape of the waveform of an applied driving voltage and the structure of a discharge cell.
Current directly flows in discharge spaces while a voltage is applied in the DC PDP, because electrodes are exposed to the discharge spaces. Therefore, a resistor for restricting the current must be used outside of the DC PDP. On the other hand, in the case of the AC PDP, the current is restricted due to the natural formation of a capacitance component because a dielectric layer covers the electrodes. The AC PDP has a longer life than the DC PDP because the electrodes are protected against the shock caused by ions during discharge.
FIG. 1 is a partial perspective view of an AC PDP.
As shown in FIG. 1, scan electrodes 4 and sustain electrodes 5 that make pairs and are covered with dielectric layer 2 and protecting film 3 are formed to be parallel to each other on first glass substrate 1. A plurality of address electrodes 8 covered with dielectric layer 7 are installed on second glass substrate 6. Barrier ribs 9 are formed to be parallel to address electrodes 8 on dielectric layer 7 between address electrodes 8. Phosphor 10 is formed on the surface of dielectric layer 7 and on both sides of barrier ribs 9. First glass substrate 1 and second glass substrate 6 are arranged to face each other interposing discharge spaces 11 between first glass substrate 1 and second glass substrate 6, so that scan electrodes 4 and sustain electrodes 5 that make pairs cross address electrodes 8. The discharge space positioned where scan electrode 4 and sustain electrode 5 that make a pair cross address electrodes 8 forms discharge cell 12.
FIG. 2 shows the arrangement of the electrodes of the PDP.
As shown in FIG. 2, the PDP electrodes have an m×n matrix structure. To be specific, address electrodes A1 through Am are arranged in a column direction, and n row sustain electrodes X1 through Xn and scan electrodes Y1 through Yn are arranged in a zigzag pattern in a row direction. The discharge cell shown in FIG. 2 corresponds to discharge cell 12 shown in FIG. 1.
In general, a method for driving the AC PDP includes a reset (initializing) period, a write (addressing) period, a sustain period, and an erase period.
In the reset period, the states of the respective cells are initialized in order to smoothly address the cells. In the write period, the cells that are turned on and the cells that are turned off are selected, and wall charges are accumulated on the cells that are turned on (the addressed cells). In the sustain period, discharge is performed in order to actually display pictures on the addressed cells. In the erase period, the wall charge of the cells is reduced, to thus terminate sustain discharge.
In the AC PDP, because the scan electrodes (Y electrodes) and the sustain electrodes (X electrodes) for performing sustain discharging of the AC PDP operate as capacitive load, capacitance between the scan electrodes and the sustain electrodes exists. Reactive power other than power for discharge is necessary in order to apply waveforms for the sustain discharge. A circuit for recovering and refusing the reactive power is referred to as a sustain discharge circuit or an energy recovery circuit.
The sustain discharge circuit of a conventional AC PDP and a method for driving the same will now be described.
FIGS. 3 and 4 show a conventional sustain discharge circuit and the operational waveforms of the conventional sustain discharge circuit.
The sustain discharge circuit suggested by L. F. Weber and disclosed in U.S. Pat. Nos. 4,866,349 and 5,081,400 is the sustain discharge circuit or the energy recovery circuit of the AC PDP. In the driving circuit of the AC PDP, sustain discharge circuit 10 of the X electrodes has the same structure as that of sustain discharge circuit 11 (not shown) of the Y electrodes. The sustain discharge circuit of the X electrodes will now be described for convenience' sake.
The conventional sustain discharge circuit 10 includes an energy recovery unit having two switches Sa and Sb, two diodes D1 and D2, inductor Lc, energy recovery capacitor Cc, and a sustain discharge unit having two switches Sc and Sd.
The panel is connected to a contact point between two switches Sc and Sd. The panel is depicted as equivalent capacitor Cp.
The conventional sustain discharge circuit having the above structure operates in four modes according to the switching operations of switches Sa through Sd, as shown in FIG. 4. The waveforms of current IL that flows through inductor Lc and output voltage Vp are respectively shown according to the switching operations.
In an initial stage, the voltage of both ends of the panel is maintained at 0 V because switch Sd is turned on immediately before switch Sa is turned on. At this time, energy recovery capacitor Cc is previously charged by voltage Vs/2 that is half of sustain discharge voltage Vs, so that a rush current is not generated when the sustain discharge starts.
In a state where voltage Vp of both ends of the panel is maintained at 0 V, at the point of time t0, the operation of mode 1 starts when switch Sa is turned on and switches Sb, Sc, and Sd are turned off.
In the operation periods between t0 and t1 of mode 1, an LC resonance circuit is formed with a current path of switch Sa, diode D1, inductor Lc, and plasma panel capacitor Cp. Therefore, as shown in FIG. 4, current IL that flows through inductor Lc forms a half wave due to LC resonance, and output voltage Vp of the panel slowly increases and becomes almost sustain discharge voltage Vs. The current scarcely flows through inductor Lc at the point of time where output voltage Vp of the panel becomes sustain discharge voltage Vs.
When mode 1 is completed, mode 2 starts when switches Sa and Sc are turned on and switches Sb and Sd are turned off. In the operation period between t1 and t2 of mode 2, external applied voltage Vs is directed through panel capacitor Cp through switch Sc to thus maintain output voltage Vp of the panel. At this time, zero-voltage switching is performed at t1 because the voltage of both ends of switch Sc is ideally 0.
When mode 2 is completed in a state where the discharge of output voltage Vp of the panel is maintained, mode 3 starts when switch Sb is turned on and switches Sa, Sb, and Sc are turned off.
In the operation period between t2 and t3 of mode 3, the LC resonance circuit is formed with a current path reverse to that in mode 1, that is, with the current path of plasma panel capacitor Cp, inductor Lc, diode D2, switch Sb, and energy recovery capacitor Cc. Accordingly, as shown in FIG. 4, current IL flows through inductor Lc and output voltage Vp of the panel decreases. Therefore, current IL of inductor Lc and output voltage Vp of the panel become 0 at the point of time t3.
In the operation period between t3 and t4 of mode 4, switches Sb and Sd are turned on and switches Sa and Sc are turned off. Accordingly, output voltage Vp of the panel is maintained at 0 V. When switch Sa is turned on again in this state, the process returns to the operation of mode 1. Accordingly, the operations are repeated.
In the conventional sustain discharge circuit, it is not possible for the switches to perform the zero-voltage switching due to the parasitic components of the actual circuit such as the parasitic resistance of the inductor, the parasitic resistances of the capacitor and the panel, and the conductance resistance of the switch. Accordingly, switching loss significantly increases when the switches are turned on. That is, according to the conventional sustain discharge circuit, the magnetic energy stored in inductor Lc is 0 when one terminal of the panel capacitor ideally increases to sustain discharge voltage Vs. Therefore, when the one terminal of the panel capacitor does not increase to sustain discharge voltage Vs due to the parasitic components of the actual circuit, a voltage source for increasing the voltage of the one terminal of the panel capacitor to sustain discharge voltage Vs does not exist. Therefore, it is not possible for actual switch Sc to perform the zero-voltage switching. Accordingly, the switching loss significantly increases when the switches are turned on.
Also, in the conventional sustain discharge circuit, the energy recovery capacitor Cc must always be previously charged to voltage Vs/2 right after the light emission starts. In a state where the energy recovery capacitor is not charged to voltage Vs/2, a significantly large rush current is generated when a sustain discharge pulse starts. Therefore, a protecting circuit for restricting the rush current must be additionally included.